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ISCRIZIONE |
Design Technologies for Wireless Multiprocessor Systems-on-Chip
Prof. Dr. Rainer Leupers
Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany
24 hours, 6 credits
July 16 - July 20, 2012
Dipartimento di Ingegneria dell'Informazione: Elettronica, Informatica, Telecomunicazioni, via Caruso, meeting room, ground floor
Contacts: Prof. Luca Fanucci
Abstract
The trend towards Multicore and even Many core architectures affects virtually all areas of computing today. Especially in the mobiles and consumer domains, an extremely high architectural efficiency (MIPS/Watt) is required. In order to manage the complexity of multi-billion transistor IC designs with dozens of heterogeneous processing engines, advanced Electronic System Level (ESL) tools are required. ESL can be roughly subdivided into four categories: architecture modeling and optimization, application SW mapping, simulation and verification, and efficient processing element design. After a general introduction to embedded MPSoC (Multiprocessor Systems-on-Chip) architectures and ESL technologies, the course will cover aspects from the above four domains, in particular SoC architecture exploration, embedded SW development with virtual platforms, efficient code generation for DSPs, and application-specific processing element design. The lectures will be complemented with hands-on lab sessions using modern industrial ESL tools.
Syllabus
- Multiprocessor Systems-on-Chip
- Wireless multimedia terminal
- Electronic System Level
- Systems-on-Chip architecture exploration
- Embedded Software development
- Application-specific processing elements
