nios_system

2012.03.06.16:02:42 Datasheet
Overview
  clk  nios_system
Processor
   CPU Nios II 11.1
All Components
   CPU altera_nios2 11.1
   Onchip_memory altera_avalon_onchip_memory2 11.1
   JTAG_UART altera_avalon_jtag_uart 11.1
   Interval_timer altera_avalon_timer 11.1
   sysid altera_avalon_sysid 11.1
   SDRAM altera_avalon_new_sdram_controller 11.1
   Red_LEDs altera_up_avalon_parallel_port 11.0
   Green_LEDs altera_up_avalon_parallel_port 11.0
   HEX3_HEX0 altera_up_avalon_parallel_port 11.0
   HEX7_HEX4 altera_up_avalon_parallel_port 11.0
   Slider_switches altera_up_avalon_parallel_port 11.0
   Pushbuttons altera_up_avalon_parallel_port 11.0
   Expansion_JP1 altera_up_avalon_parallel_port 11.0
   Expansion_JP2 altera_up_avalon_parallel_port 11.0
   Serial_port altera_up_avalon_rs232 11.0
   SRAM altera_up_avalon_sram 11.0
Memory Map
CPU
 instruction_master  data_master
  CPU
jtag_debug_module  0x0a000000 0x0a000000
  Onchip_memory
s1  0x09000000
s2  0x09000000
  JTAG_UART
avalon_jtag_slave  0x10001000
  Interval_timer
s1  0x10002000
  sysid
control_slave  0x10002020
  SDRAM
s1  0x00000000 0x00000000
  Red_LEDs
avalon_parallel_port_slave  0x10000000
  Green_LEDs
avalon_parallel_port_slave  0x10000010
  HEX3_HEX0
avalon_parallel_port_slave  0x10000020
  HEX7_HEX4
avalon_parallel_port_slave  0x10000030
  Slider_switches
avalon_parallel_port_slave  0x10000040
  Pushbuttons
avalon_parallel_port_slave  0x10000050
  Expansion_JP1
avalon_parallel_port_slave  0x10000060
  Expansion_JP2
avalon_parallel_port_slave  0x10000070
  Serial_port
avalon_rs232_slave  0x10001010
  SRAM
avalon_sram_slave  0x08000000 0x08000000

clk

clock_source v11.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

CPU

altera_nios2 v11.1
clk clk   CPU
  clk
instruction_master   Onchip_memory
  s1
data_master  
  s2
data_master   JTAG_UART
  avalon_jtag_slave
d_irq  
  irq
data_master   Interval_timer
  s1
d_irq  
  irq
data_master   sysid
  control_slave
instruction_master   SDRAM
  s1
data_master  
  s1
data_master   Serial_port
  avalon_rs232_slave
d_irq  
  interrupt
data_master   Expansion_JP2
  avalon_parallel_port_slave
d_irq  
  interrupt
data_master   Expansion_JP1
  avalon_parallel_port_slave
d_irq  
  interrupt
data_master   Pushbuttons
  avalon_parallel_port_slave
d_irq  
  interrupt
data_master   Slider_switches
  avalon_parallel_port_slave
data_master   HEX7_HEX4
  avalon_parallel_port_slave
data_master   HEX3_HEX0
  avalon_parallel_port_slave
data_master   Green_LEDs
  avalon_parallel_port_slave
data_master   Red_LEDs
  avalon_parallel_port_slave
data_master   SRAM
  avalon_sram_slave
instruction_master  
  avalon_sram_slave


Parameters

userDefinedSettings
tightlyCoupledInstructionMaster3MapParam
tightlyCoupledInstructionMaster3AddrWidth 1
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledDataMaster3MapParam
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster0AddrWidth 1
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Static
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave SDRAM.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _10
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 7427
instSlaveMapParam <address-map><slave name='SDRAM.s1' start='0x0' end='0x800000' /><slave name='SRAM.avalon_sram_slave' start='0x8000000' end='0x8080000' /><slave name='Onchip_memory.s1' start='0x9000000' end='0x9002000' /><slave name='CPU.jtag_debug_module' start='0xA000000' end='0xA000800' /></address-map>
instAddrWidth 28
impl Tiny
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave SDRAM.s1
exceptionOffset 32
deviceFeaturesSystemInfo ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
deviceFamilyName Cyclone II
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _4
dcache_bursts false
dataSlaveMapParam <address-map><slave name='SDRAM.s1' start='0x0' end='0x800000' /><slave name='SRAM.avalon_sram_slave' start='0x8000000' end='0x8080000' /><slave name='Onchip_memory.s2' start='0x9000000' end='0x9002000' /><slave name='CPU.jtag_debug_module' start='0xA000000' end='0xA000800' /><slave name='Red_LEDs.avalon_parallel_port_slave' start='0x10000000' end='0x10000010' /><slave name='Green_LEDs.avalon_parallel_port_slave' start='0x10000010' end='0x10000020' /><slave name='HEX3_HEX0.avalon_parallel_port_slave' start='0x10000020' end='0x10000030' /><slave name='HEX7_HEX4.avalon_parallel_port_slave' start='0x10000030' end='0x10000040' /><slave name='Slider_switches.avalon_parallel_port_slave' start='0x10000040' end='0x10000050' /><slave name='Pushbuttons.avalon_parallel_port_slave' start='0x10000050' end='0x10000060' /><slave name='Expansion_JP1.avalon_parallel_port_slave' start='0x10000060' end='0x10000070' /><slave name='Expansion_JP2.avalon_parallel_port_slave' start='0x10000070' end='0x10000080' /><slave name='JTAG_UART.avalon_jtag_slave' start='0x10001000' end='0x10001008' /><slave name='Serial_port.avalon_rs232_slave' start='0x10001010' end='0x10001018' /><slave name='Interval_timer.s1' start='0x10002000' end='0x10002020' /><slave name='sysid.control_slave' start='0x10002020' end='0x10002028' /></address-map>
dataAddrWidth 29
customInstSlavesSystemInfo <info/>
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave CPU.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "tiny"
BIG_ENDIAN 0
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x20
RESET_ADDR 0x0
BREAK_ADDR 0xa000020
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_MULTIPLY_PRESENT 0
HARDWARE_MULX_PRESENT 0
HARDWARE_DIVIDE_PRESENT 0
INST_ADDR_WIDTH 28
DATA_ADDR_WIDTH 29

Onchip_memory

altera_avalon_onchip_memory2 v11.1
clk clk   Onchip_memory
  clk2
clk  
  clk1
CPU instruction_master  
  s1
data_master  
  s2


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName Onchip_memory
blockType M4K
dataWidth 32
deviceFamily Cyclone II
dualPort true
initMemContent true
initializationFileName Onchip_memory
instanceID NONE
memorySize 8192
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "Onchip_memory"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "M4K"
WRITABLE 1
DUAL_PORT 1
SINGLE_CLOCK_OP 0
SIZE_VALUE 8192u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "M4K"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

JTAG_UART

altera_avalon_jtag_uart v11.1
clk clk   JTAG_UART
  clk
CPU data_master  
  avalon_jtag_slave
d_irq  
  irq


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

Interval_timer

altera_avalon_timer v11.1
clk clk   Interval_timer
  clk
CPU data_master  
  s1
d_irq  
  irq


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 125.0
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 50000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 125.0
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 50000000u
LOAD_VALUE 6249999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 8u

sysid

altera_avalon_sysid v11.1
clk clk   sysid
  clk
CPU data_master  
  control_slave


Parameters

id 0
timestamp 1331046157
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 0u
TIMESTAMP 1331046157u

SDRAM

altera_avalon_new_sdram_controller v11.1
clk clk   SDRAM
  clk
CPU instruction_master  
  s1
data_master  
  s1


Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 50000000
columnWidth 8
dataWidth 16
generateSimulationModel false
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
registerDataIn true
rowWidth 12
size 8388608
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 0
SDRAM_DATA_WIDTH 16
SDRAM_ADDR_WIDTH 22
SDRAM_ROW_WIDTH 12
SDRAM_COL_WIDTH 8
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 15.625
POWERUP_DELAY 100.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

Red_LEDs

altera_up_avalon_parallel_port v11.0
CPU data_master   Red_LEDs
  avalon_parallel_port_slave
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset LEDs
leds Red
sevensegs 3 to 0
gpio GPIO 0 (JP1)
DW 18
direction Output only
custom_DW 32
custom_direction Input only
capture false
edge Rising
irq false
irq_type Level
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Green_LEDs

altera_up_avalon_parallel_port v11.0
CPU data_master   Green_LEDs
  avalon_parallel_port_slave
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset LEDs
leds Green
sevensegs 3 to 0
gpio GPIO 0 (JP1)
DW 9
direction Output only
custom_DW 32
custom_direction Input only
capture false
edge Rising
irq false
irq_type Level
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

HEX3_HEX0

altera_up_avalon_parallel_port v11.0
CPU data_master   HEX3_HEX0
  avalon_parallel_port_slave
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset Seven Segment Displays
leds Green
sevensegs 3 to 0
gpio GPIO 0 (JP1)
DW 32
direction Output only
custom_DW 32
custom_direction Input only
capture false
edge Rising
irq false
irq_type Level
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

HEX7_HEX4

altera_up_avalon_parallel_port v11.0
CPU data_master   HEX7_HEX4
  avalon_parallel_port_slave
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset Seven Segment Displays
leds Green
sevensegs 7 to 4
gpio GPIO 0 (JP1)
DW 32
direction Output only
custom_DW 32
custom_direction Input only
capture false
edge Rising
irq false
irq_type Level
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Slider_switches

altera_up_avalon_parallel_port v11.0
CPU data_master   Slider_switches
  avalon_parallel_port_slave
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset Slider Switches
leds Green
sevensegs 3 to 0
gpio GPIO 0 (JP1)
DW 18
direction Input only
custom_DW 32
custom_direction Input only
capture false
edge Rising
irq false
irq_type Level
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Pushbuttons

altera_up_avalon_parallel_port v11.0
CPU data_master   Pushbuttons
  avalon_parallel_port_slave
d_irq  
  interrupt
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset Pushbuttons
leds Green
sevensegs 3 to 0
gpio GPIO 0 (JP1)
DW 4
direction Input only
custom_DW 32
custom_direction Input only
capture true
edge Falling
irq true
irq_type Edge
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Expansion_JP1

altera_up_avalon_parallel_port v11.0
CPU data_master   Expansion_JP1
  avalon_parallel_port_slave
d_irq  
  interrupt
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset Expansion Header
leds Green
sevensegs 3 to 0
gpio GPIO 0 (JP1)
DW 32
direction Bidirectional (tri-state)
custom_DW 32
custom_direction Input only
capture true
edge Falling
irq true
irq_type Edge
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Expansion_JP2

altera_up_avalon_parallel_port v11.0
CPU data_master   Expansion_JP2
  avalon_parallel_port_slave
d_irq  
  interrupt
clk clk  
  clock_reset


Parameters

board DE2
custom_port false
preset Expansion Header
leds Green
sevensegs 3 to 0
gpio GPIO 1 (JP2)
DW 32
direction Bidirectional (tri-state)
custom_DW 32
custom_direction Input only
capture true
edge Falling
irq true
irq_type Edge
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Serial_port

altera_up_avalon_rs232 v11.0
CPU data_master   Serial_port
  avalon_rs232_slave
d_irq  
  interrupt
clk clk  
  clock_reset


Parameters

baud 115200
parity Odd
data_bits 8
stop_bits 1
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

SRAM

altera_up_avalon_sram v11.0
CPU data_master   SRAM
  avalon_sram_slave
instruction_master  
  avalon_sram_slave
clk clk  
  clock_reset


Parameters

board DE2
pixel_buffer false
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)
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