A list of my publications

(The authors of the publications marked with * are listed in alphabetical order)

Journals

2014

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-based FPGAs
C. Bernardeschi, L. Cassano, A. Domenici, and L. Sterpone
To appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (*)

Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-ion Batteries
F. Baronti, C. Bernardeschi, L. Cassano, A. Domenici, R. Roncella, R. Saletti
In IEEE Transactions on Industrial Informatics (*)

2013

GABES: a Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs
C. Bernardeschi, L. Cassano, M.G.C.A. Cimino, A. Domenici
In Journal of Systems Architecture, vol. 59, issue 10, part D, November 2013, pag. 1243-1254 (*)

2011

Simulation and Test-Case Generation for PVS Specifications of Control Logics
C. Bernardeschi, L. Cassano, A. Domenici, P. Masci
In International Journal On Advances in Software, vol. 5, nr. 1&2 (*)

Conferences

2014

Early Assessment of SEU Sensitivity through Untestable Faults Identification
Luca Cassano, Hipolito Guzman-Miranda and Miguel Angel Aguirre
Accepted at IOLTS 2014 the 20th IEEE International On-Line Testing Symposium, Platja d'Aro, Catalunya, Spain, July 7-9, 2014

Detecting Possible Locations for Hardware Trojans by Identifying Untestable Faults
Cristiana Bolchini and Luca Cassano
Accepted at TRUDEVICE 2014 the 2nd Workshop on Test and Fault Tolerance for Secure Devices, Paderborn, Germany, May 29-30, 2014 (*)

An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems
Luca Cassano, Dario Cozzi, Dirk Jungewelter, Sebastian Korf, Jens Hagemeyer, Mario Porrmann and Cinzia Bernardeschi
Accepted at DTIS 2014 the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, May 6-8, 2014

A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMR
Luca Cassano, Alberto Bosio and Giorgio Di Natale
Accepted at ETS 2014 the 19th IEEE European Test Symposium, Paderborn, Germany, May 26-30, 2014

Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations
Daniel Cesarini, Luca Cassano, Alessio Fagioli and Marco Avvenuti
In ES4CPS 2014 the DATE 2014 Workshop on Engineering Simulations for Cyber-Physical Systems, Bremen, Germany, March 28, 2014

2013

Mitigation of Single Event Upsets in the Control Logic of a Charge Equalizer for Li-ion Batteries
Federico Baronti, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Roberto Roncella, Roberto Saletti
In IECON 2013 the 39th Annual Conference of the IEEE Industrial Electronics Society, Vienna, Austria, November 10-13, 2013 (*)

Simulation of Automatic Weather Stations for the Energy Estimation of Sensing and Communication Software Policies
Marco Avvenuti, Luca Cassano, Daniel Cesarini and Silvia Mandalá
In ExtremeCom 2013, The 5th Extreme Conference on Communication, Iceland, August 24-30, 2013 (*)

Formal approaches to SEU testing in FPGAs
Cinzia Bernardeschi, Luca Cassano and Andrea Domenici
In AHS 2013, The NASA/ESA Conference on Adaptive Hardware and Systems, Torino, Italy, June 25-27, 2013 (*)

Unexcitability Analysis of SEUs Affecting the Routing Structure of SRAM-based FPGAs
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici and Luca Sterpone
In GLSVLSI 2013, The 23rd Great Lakes Symposium on Very Large Scale of Integration, Paris, France, May 2-3, 2013 (*)

On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems
Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann and Luca Sterpone
In DATE 2013, Design Automation & Test in Europe, Grenoble, France, March 18-22, 2013

2012

Accurate Simulation of SEUs in the Configuration Memory of SRAM-based FPGAs
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
In DFT 2012, The 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Austin, Texas, USA, October 3-5, 2012 (*)

SEU-X: a SEu Un-eXcitability prover for SRAM-FPGAs
C. Bernardeschi, L. Cassano, A. Domenici
In IOLTS 2012, The 18th IEEE International On-Line Testing Symposium, Sitges, Spain, June 27-29, 2012 (*)

Application of a Genetic Algorithm for Testing SEUs in SRAM-FPGA Systems
C. Bernardeschi, L. Cassano, M.G.C.A. Cimino, A. Domenici
In WRC 2012, The 6th HiPEAC Workshop on Reconfigurable Computing, Paris, France, January 24, 2012 (*)

2011

Simulated Injection of Radiation-Induced Logic Faults in FPGAs
C. Bernardeschi, L. Cassano, A. Domenici, G. Gennaro, M. Pasquariello
In VALID 2011, The Third International Conference on Advances in System Testing and Validation Lifecycle, Barcelona, Spain, October 23-28, 2011 (*)

A Tool for Signal Probability Analysis of FPGA-Based Systems (Winner of the best paper award)
C. Bernardeschi, L. Cassano, A. Domenici, P. Masci
In COMPUTATION TOOLS 2011, The Second International Conference on Computational Logics, Algebras, Programming, Tools, and Benchmarking, Rome, Italy, September 25-30, 2011 (*)

Failure Probability and Fault Observability of SRAM-FPGA Systems
C. Bernardeschi, L. Cassano, A. Domenici
In FPL 2011, the 21st International Conference on Field Programmable Logic and Applications, Chania, Crete, Greece, September 5-7, 2011 (*)

Failure Probability of SRAM-FPGA Systems with Stochastic Activity Networks
C. Bernardeschi, L. Cassano, A. Domenici
In DDECS 2011, the 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, Germany, April 13-15, 2011 (*)[pdf][bibtex]

2010

Debugging PVS Specifications of Control Logics via Event-driven Simulation (Winner of the best paper award)
C. Bernardeschi, L. Cassano, A. Domenici, P. Masci
In COMPUTATION TOOLS 2010, the First International Conference on Computational Logics, Algebras, Programming, Tools, and Benchmarking, Lisbon, Portugal, November 21-26, 2010. (*)[pdf][bibtex]

Other Talks

2014

Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
Luca Cassano
In the 2014 E.J. McCluskey Doctoral Thesis Award Semifinals Located at ETS 2014, Paderborn, Germany, May 26-30, 2014

Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
Luca Cassano
In the EDAA/ACM SIGDA PhD Forum at DATE 2014, Bremen, Germany, March 24-28, 2014

2013

A CAD Flow for On-Line Testing and Patching Permanent Radiation Effects in Reconfigurable Systems
Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann and Luca Sterpone
In the SEE/MAPLD 2013 joint session of the Single Event Effects Symposium and Military and Aerospace Programmable Logic Devices Conference, San Diego, California, USA, April 9-12, 2013

2012

A CAD Flow for the Analysis of the Sensitivity to SEUs of SRAM-FPGAs
Luca Cassano
In SEFUW 2012, The 1st ESA SpacE FPGA Users Workshop, Nordwjik, The Netherlands, November 6-7, 2012




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